High Reliable FPGA Based System Design Methodology

This paper describes a methodology of the automatic design process for the concurrent error detection (CED) circuits based on FPGAs. Our solution assumes the possibility of dynamical reconfiguration of the faulty part. The most important criterion is the speed of the fault detection and the safety of the whole circuit with respect to the surrounding environment. Our methodology enables cooperation between on-line and off-line BIST for fault detection and localization. The concurrent error detection (CED) design methodology used to satisfy TSC property has a deep impact on the fault coverage of circuits implemented in FPGAs. Basic methods used for the fault detection in logic circuits are based on simple duplication. This methodology tries to determine the final area overhead before the circuit is duplicated. The duplicate part can be modified to avoid common-mode failures (CMFs). Another approach can be used where the duplicate circuit is modified to decrease the number of outputs of the duplicate part (output parity bits are used instead original outputs). Error detecting codes can be used in this case. Both of these techniques are compared in [4]. There are two main reasons why the CED techniques were not so popular in the past: Very high area overhead and low disposition to temporary faults due to their large feature sizes. Some of the new design methods try to reach smaller area overhead but they achieve low fault detection. For example, only some inputs may be used to ensure the partial self-checking property of a multilevel logic, by using low-cost parity error detecting codes [5]. The next different design methodology ensuring smaller area overhead uses duplication of only some parts of the original circuit. This method is based on the reduction of the number of selected input combinations [2]. Some articles describe methods how to detect the faulty part of an FPGA without stopping its function [1]. These methods test unused parts of the FPGA. When the test is performed, the tested part is exchanged with the used part and the testing process is started again for currently unused area.